三维沟槽阵列 MOS 电容结构的电容特性仿真研究
首发时间:2026-03-16
摘要:为提高硅基电容器的单位面积电容密度,开展三维沟槽阵列 MOS 电容结构的数值仿真研究。以平行板 MOS 电容为对照结构,利用 Sentaurus TCAD 平台构建 PolySi/HfO2/Si 器件模型,并通过参数化方法建立三维圆孔阵列沟槽 MOS 电容结构。在统一工艺参数条件下,对两种结构进行低频 C-V 特性仿真,同时系统分析沟槽深度H、介质层厚度t 及沟槽半径R 等关键结构参数对单位面积电容密度的影响规律。仿真结果表明,相比传统平行板 MOS 电容结构,三维沟槽阵列结构通过增加侧壁有效电极面积,可显著提升电容密度,在H=3μm、t=15nm、R=0.3μm 条件下,电容密度由 14.83 nF/mm2 提升至 115.89 nF/mm2。进一步研究发现,增大沟槽深度和减小介质层厚度均可明显提高电容密度,而在保持阵列周期比例关系 P=3R 条件下,减小沟槽半径有利于提高阵列填充率,从而提升单位面积电容性能。研究结果表明,三维沟槽阵列结构在提高硅基电容器电容密度方面具有显著优势,可为高密度集成电容器的结构设计与优化提供理论参考。
关键词: 微电子学 MOS电容 三维沟槽结构 电容密度 Sentaurus TCAD
For information in English, please click here
Simulation Study on Capacitive Characteristics of Three-Dimensional Trench Array MOS Capacitor Structure
Abstract:To improve the capacitance density per unit area of silicon-based capacitors, a numerical simulation study of a three-dimensional trench array MOS capacitor structure was conducted. Using a parallel-plate MOS capacitor as a control structure, a PolySi/HfO?/Si device model was constructed using the Sentaurus TCAD platform, and a three-dimensional circular aperture array trench MOS capacitor structure was established using a parametric method. Under unified process parameters, low-frequency C-V characteristic simulations were performed on both structures. Simulation results also systematically analyzed the influence of key structural parameters such as trench depth H, dielectric layer thickness t, and trench radius R on the capacitance density per unit area. The simulation results show that compared to the traditional parallel-plate MOS capacitor structure, the three-dimensional trench array structure significantly improves the capacitance density by increasing the effective electrode area on the sidewalls. Under the conditions of H=3μm, t=15nm, and R=0.3μm, the capacitance density increases from 14.83 nF/mm2 to 115.89 nF/mm2. Further research revealed that increasing the trench depth and decreasing the dielectric layer thickness both significantly improve capacitance density. While maintaining the array period ratio P=3R, reducing the trench radius is beneficial for increasing the array fill rate, thereby enhancing capacitance performance per unit area. The results demonstrate that three-dimensional trench array structures have significant advantages in improving the capacitance density of silicon-based capacitors, providing a theoretical reference for the structural design and optimization of high-density integrated capacitor.
Keywords: Microelectronics MOS capacitors three-dimensional trench structure capacitance density Sentaurus TCAD
基金:
引用

No.****
动态公开评议
共计0人参与
勘误表
三维沟槽阵列 MOS 电容结构的电容特性仿真研究
评论
全部评论