An In-Memory Computing Full Adder Design Based 6T SRAM

• 1、Integrated Circuits School, Dalian University of Technology, Dalian 16620

Abstract：In this paper a new memory computing circuit structure is proposed, which can realize the function of full adder in 6T SRAM memory and provide flexible hop logic operation in multi-bit computing. The 6T SRAM register is designed and extended by multi-logic gate combination, and the circuit implementation of 8-bit memory full adder is presented. In addition, combined with the innovative design of advance carry addition and adaptive skip logic, the computing performance of the memory full adder is further improved and the power balance is achieved. In the 28nm CMOS process, based on 1V operating voltage, the typical operating delay of the 8-bit 6T SRAM memory full adder is 129.6 ps and the throughput reaches 22.30GOPS. The design scheme achieves a good balance in improving the computing speed and power consumption control, and has significant advantages in the requirements of high performance, high computing and low power consumption of on-board SOCs.

Keywords： In memory computing Adaptive carry management In memory full adder 6T SRAM