Optimization and research of ShuffleNetV2 accelerator based on FPGA

• 1、School of Electronic Engineering, Beijing University of Posts and Telecommunications,Beijing,100876

Abstract：In the rapidly advancing field of artificial intelligence, the demands for neural network training and inference are increasingly substantial. Particularly in various application scenarios such as edge devices and embedded systems, like face recognition, voice recognition, and autonomous driving, there often arises a situation of limited resources, including power consumption, memory, and computational capacity. To address the issue of hardware resource constraints, a neural network accelerator based on FPGA was designed. This accelerator focuses on the mainstream lightweight convolutional neural network, ShuffleNetV2, introducing improvements that include 16-bit model quantization. It also redesigns the construction blocks and shuffle operations of ShuffleNetV2 for a hardware-friendly design. The optimized model was deployed on a ZYNQ-7020 board. Experiments show that, with less than 1% loss in accuracy, the optimized ShuffleNetV2 model achieves a 0.4ms speed improvement over GPU, a 7.3 times speed increase over CPU, and reaches 4.05 GOPs, with power consumption only at 2.663W, resulting in an energy efficiency of 1.54 GOPs/W. The latency of the optimized model is 43ms, which is 42% of the baseline.

Keywords： Lightweight convolutional neural network FPGA Energy efficiency ratio Heterogeneous acceleration