Thermal analysis of HTCP based on compact thermal resistance network

• 1、National Key Lab of Micor/Nano Fabrication Technology, Institute of Microelectronics, Peking University, Beijing, China, 100871
• 2、Peking University Shenzhen Graduate School, Shenzhen, 518055

Abstract：This paper studies a simplified but accurate calculation method of high thermal conductivity path constructed by thermal through-silicon-via (T-TSV), thermal-wire (T-wire) and Micro-bump in the thermal management of three-dimensional integrated circuit (3D IC). Thermal management of 3D IC can be decomposed into two typical subsystem where intra-layer and inter-layer hot-spots are considered individually. The intra-layer hot-spot refers to a block of power unit and its interconnections, which contacts the high thermal conductivity silicon. While, the inter-layer hot-spot in this work is micro-bump with high thermal loads, which is an equivalent hot-spot without heat generation but transferring most heat from the upper layers. Thermal problem appears in inter-layer hot-spot case because of relatively low thermal conductivity of inter-layer dielectric. Thermal resistance network of T-TSV and T-wire, which are connected directly to inter-layer hot-spots, are proposed based on individual calculation of each part. Based on the result of calculation of T-TSV and T-wire, thermal analysis of the whole high thermal conductivity path is available. The simplified calculation method display a difference less than 3% compared with the numerical simulation of the same model.

Keywords： Microelectronics High thermal conductivity paht Compact thermal resistance network TSV