Design and Implementation of DPLL Based on Single-chip CPLD

• 1、School of Information Engineering,Wuhan University Of Technology,WuHan 430070

Abstract：With the development of digital circuit technology, digital phase-locked loop frequency synthesizer, carrier synchronization, and other aspects of modems are widely used. This paper presents a novel based on the DPLL CPLD. The high-precision digital phase locked loop by the counter module, 32-bit divider module, frequency signal generator module, signal divider, phase measuring module, the counting module compensation, phase compensation module, interface control module is a new design ideas. The phase-locked loop PLL compared to the general, the important feature is the realization of the low frequency signal and locked multiplier and multiplier value can be set in real time through a variety of interfaces, and a phase locked output square wave signal It can be preset to 0 or 90 . All algorithms can be loaded into a CPLD chip, so CPLD chip is customized to a digital PLL chip, to facilitate the application to a variety of digital phase locked loop circuit is used.

Keywords： DPLL clock multiplier single-chip CPLD